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55-nm IoT Platform

September 20, 2017 - This demonstration features an ASIC platform that significantly increases performance, lowers power consumption and reduces system cost for always-on IoT applications. It showcase applications such...

65LPe-Common Platform Datasheet

Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and a full set of logic libraries optimized for the Common Platform 65LPe process.

7-nm Design Tips for Performance, Power & Area Optimization

April 27, 2017 - Learn how to combine the benefits of 7-nm processes with optimized embedded memories and standard cells to develop the most competitive SoCs.

7-nm Design Tips for Performance, Power & Area Optimization - China

August 08, 2017 - Learn how to combine the benefits of 7-nm processes with optimized embedded memories and standard cells to develop the most competitive SoCs.

7-nm Design Tips for Performance, Power & Area Optimization - Taiwan

August 08, 2017 - Learn how to combine the benefits of 7-nm processes with optimized embedded memories and standard cells to develop the most competitive SoCs.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet

This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...

A Method to Quickly Assess the Analog Front-End Performance in Communication ...

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the ...