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55-nm IoT Platform

September 20, 2017

65LPe-Common Platform Datasheet

Broad portfolio of HS, HD and LP memory compilers and a full set of logic libraries optimized for CP 65LPe

7-nm DesignWare 56G Ethernet PHY IP Performance Results

September 04, 2019 - This video shows the performance and capabilities of Synopsys’ DesignWare 56G Ethernet PHY IP in 7-nm FinFET process.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet

This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...

A Method to Quickly Assess the Analog Front-End Performance in Communication ...

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the ...

A Survival Guide for Selecting High-Quality IP

In this paper we will explore three important determinants of IP quality.

Abilis Achieves First-Pass Silicon Success for Secure Media Processor Using ...

Abilis was able to fulfill their time-to-market requirements with Synopsys’ silicon-proven DesignWare Interface IP, ARC Processors and tools, Synopsys’ consulting services and Lynx Design System.