April 20, 2017
September 20, 2017
Broad portfolio of HS, HD and LP memory compilers and a full set of logic libraries optimized for CP 65LPe
September 04, 2019 - This video shows the performance and capabilities of Synopsys’ DesignWare 56G Ethernet PHY IP in 7-nm FinFET process.
December 17, 2015
This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...
This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the ...
In this paper we will explore three important determinants of IP quality.
Abilis was able to fulfill their time-to-market requirements with Synopsys’ silicon-proven DesignWare Interface IP, ARC Processors and tools, Synopsys’ consulting services and Lynx Design System.