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55-nm IoT Platform

September 20, 2017

56G 112G Ethernet and Die-to-Die PHY IP Essentials

April 15, 2020 - Simplified Chinese: If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast ...

56G 112G Ethernet and Die-to-Die PHY IP Essentials

April 15, 2020 - Traditional Chinese: If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast ...

56G/112G Ethernet and Die-to-Die PHY IP Essentials

January 29, 2020 - If you are designing high-performance compute and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is...

65LPe-Common Platform Datasheet

Broad portfolio of HS, HD and LP memory compilers and a full set of logic libraries optimized for CP 65LPe

7-nm DesignWare 56G Ethernet PHY IP Performance Results

September 04, 2019 - This video shows the performance and capabilities of Synopsys’ DesignWare 56G Ethernet PHY IP in 7-nm FinFET process.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet

This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...