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On-Chip Clock and Process Monitoring Using STAR Hierarchical System’s ...

DesignWare® STAR Hierarchical System’s Measurement Unit has clock and process monitoring capabilities that track embedded sensors & monitors and can record and confirm that measurements meet ...

Rapid Pattern Sequencing and Optimization with STAR Hierarchical System at ...

This white paper is the second of two papers on STMicroelectronics’ experience with the DesignWare® SHS. The paper provides insights on IEEE 1500 based network implementation, execution & analysis.

STMicroelectronics' Implementation of the STAR Hierarchical System and IEEE ...

This white paper discusses how STMicroelectronics implemented the IEEE 15000 wrapping architecture through the use of Synopsys’ DesignWare® STAR Hierarchical System test solution.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet

This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...

ARC HS4x and HS4xD CPUs: New Dual-Issue Architecture Boosts Embedded ...

This white paper describes the Synopsys DesignWare® ARC® HS4x and HS4xD series of licensable CPU cores.

Saving Power in a UFS Implementation Leveraging MIPI M-PHY and UniPro

The JEDEC Universal Flash Storage (UFS) has become the mobile storage standard of choice for today’s high-end smartphones and tablets mainly due to the specification’s performance and power ...

The Basics of Foundation IP for Automotive ICs

Understand the functional safety, reliability and quality standards for automotive ICs, and how embedded memories and logic libraries can influence your product’s success.

Assessing ESD Sensitivity of Interface IP Using Charged Device Model

This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM ...

Three Power Saving Techniques Using PCI Express IP

This paper uses PCI Express IP as an example to describe three power saving techniques and how designers are using the protocol’s and design tools’ power management features to deliver ...

Software Development Kits (SDKs) for Proprietary Processors

Using ASIP Designer to generate an SDK minimizes the effort and cost of SDK development, maximizes SDK capabilities, and allows the design team to focus their efforts on architectural optimizations.