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USB 3.2: The Latest USB Type-C Challenge for SoC Designers

This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the latest USB 3.2 specification for USB Type-C™, and explains how the latest specification affects...

Right-sizing your Cryptographic Processing Solution

This white paper presents implementation options for cryptographic security algorithms, as well as a method to right-size your cryptographic processing solution by benchmarking and comparing ...

IP for Centralized ADAS Domain Controllers

This white paper describes the new ADAS SoC architecture which has transitioned from decentralized ECUs to centralized multi-domain controllers and explains the implementation of domain controllers...

The Impact of AI on Autonomous Vehicles

One of the key enablers of vehicle autonomy moving forward will be the application of AI techniques, particularly those based upon deep-learning algorithms implemented on multi-layer CNNs. These ...

Data Converters IP for Automotive SoCs

Meet automotive requirements by judicious partitioning of the functional safety requirements between the IP, such as data converters, and the SoC functional blocks that include the IP.

On-Chip Clock and Process Monitoring Using STAR Hierarchical System’s ...

DesignWare® STAR Hierarchical System’s Measurement Unit has clock and process monitoring capabilities that track embedded sensors & monitors and can record and confirm that measurements meet ...

Rapid Pattern Sequencing and Optimization with STAR Hierarchical System at ...

This white paper is the second of two papers on STMicroelectronics’ experience with the DesignWare® SHS. The paper provides insights on IEEE 1500 based network implementation, execution & analysis.

STMicroelectronics' Implementation of the STAR Hierarchical System and IEEE ...

This white paper discusses how STMicroelectronics implemented the IEEE 15000 wrapping architecture through the use of Synopsys’ DesignWare® STAR Hierarchical System test solution.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet

This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, ...

ARC HS4x and HS4xD CPUs: New Dual-Issue Architecture Boosts Embedded ...

This white paper describes the Synopsys DesignWare® ARC® HS4x and HS4xD series of licensable CPU cores.