IP Resources

Synopsys Suggests

Assessing ESD Sensitivity of Interface IP Using Charged Device Model

This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM ...

Three Power Saving Techniques Using PCI Express IP

This paper uses PCI Express IP as an example to describe three power saving techniques and how designers are using the protocol’s and design tools’ power management features to deliver ...

Software Development Kits (SDKs) for Proprietary Processors

Using ASIP Designer to generate an SDK minimizes the effort and cost of SDK development, maximizes SDK capabilities, and allows the design team to focus their efforts on architectural optimizations.

High Performance and Scalable Sensor Connectivity with MIPI I3C

This paper describes the MIPI I3C specification and its key benefits for a seamless transition from I2C to I3C.

White Paper: Securing the Internet of Things Using Hardware Rooted Processor ...

This paper can help you decide on the optimal mix of features and best tradeoffs to make for your specific IoT device that will result in a secure architecture that can be efficiently implemented.

Foundation IP for 7nm FinFETs: Design and Implementation

Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical ...

Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures

This white paper explains how LPDDR4 is different from all previous JEDEC DRAM specifications.

Addressing Three Critical Challenges of USB Type-C Implementation

This white paper describes these key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.

Designing an Efficient DSP Solution: Choosing the Right Processor and ...

This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with...

Delivering High Quality Analog Video Signals with Optimized Video DACs

The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.