IP Resources

Synopsys Suggests

How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10 ...

https://www.synopsys.com/dw/doc.php/wp/10g_ethernet_wp.pdf

This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys’ complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target ...

Ultra Low-Power 9D Sensor Fusion Implementation White Paper

https://www.synopsys.com/dw/doc.php/wp/9d_sensor_fusion_implementation.pdf

Learn how to implement a power-efficient 9D fusion algorithm on an IP subsystem: a processor core that is augmented with hardware accelerators.

Addressing IP Integration & Software Development Challenges to Accelerate SoC...

https://www.synopsys.com/dw/doc.php/wp/accelerated_ip_addressing_challenges_wp_chinese.pdf

This white paper will explore the issues facing SoC designers as they address SoC complexity and time-tomarket challenges. It will discuss the use of third-party IP while noting that high-quality ...

Reduce Power, Area and Routing Congestion - Analysis of a High-Performance ...

https://www.synopsys.com/dw/doc.php/wp/amba_hybrid_wp.pdf

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while ...

Rapid Architectural Exploration in Designing Application-Specific Processors ...

https://www.synopsys.com/dw/doc.php/wp/architectural_exploration_designing_application_specific_processors.pdf

This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability...

Designing an Efficient DSP Solution: Choosing the Right Processor and ...

https://www.synopsys.com/dw/doc.php/wp/arc_dsp_solution_wp.pdf

This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with...

Synopsys DesignWare ARC EM Family: Efficient CPU Cores for Embedded ...

https://www.synopsys.com/dw/doc.php/wp/arc_em_linley_wp.pdf

This report, prepared by the Linley Group shows that according to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high ...

ARC HS38: Single- and Multicore CPUs for High-Speed Linux Processing on an ...

https://www.synopsys.com/dw/doc.php/wp/arc_hs38_linley_wp.pdf

This report by the Linley Group describes the Synopsys DesignWare® ARC® HS38 multicore processor for embedded Linux applications.

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded ...

https://www.synopsys.com/dw/doc.php/wp/arc_hs_linley_wp.pdf

The Linley Group prepared this report on the ARC HS34 and HS36 processors after evaluating ARC HS performance data and technical features.

White Paper: Obfuscating Attacks on Secure SoCs through Encrypted Code Execution

https://www.synopsys.com/dw/doc.php/wp/arc_secure_wp.pdf

By enabling on-the-fly execution of encrypted code, the ARC Secure option for DesignWare ARC 600 processors ensures that attacks accessing instruction memory contents find encrypted code, and ...