IP Resources

Synopsys Suggests

Modeling, Measurement, and Verification of PCI Express® 4.0 (Synopsys and...

http://event.on24.com/r.htm?e=1047145&s=1&k=E6FFD15892EE7B0773D03C6D0E583327&partnerref=Synopsys&cmp=WEBR-dwip100471-HPW

Learn about the IBIS-AMI model & how PHY features and performance are implemented into the model. See a comparison between IBIS-AMI simulation results & silicon measurements for a 16Gbps PCIe 4.0 ...

LPDDR4 Multi-Channel Architecture

http://seminar2.techonline.com/registration/distrib.cgi?s=2192&d=4111&cmp=WEBR-dwip100392-HPW

Learn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.

How to Optimize your Application-Specific Processor (ASIP)

http://webinar.techonline.com/19364?keycode=CAA1CC&cmp=WEBR-proc100397-HPW

Attend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys' ASIP design tool.

Achieving Energy Efficiency for IoT Designs

http://webinar.techonline.com/19365?keycode=CAA1CC&cmp=WEBR-dwip100401-HPW

Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.

Understanding USB 3.1’s Physical, Link & Protocol Layer Changes

http://webinar.techonline.com/19413?keycode=CAA1CC&cmp=WEBR-dwip100398-HPW

Get an in-depth look at the changes in the USB 3.1 specification’s physical layer, link layer, protocol layer, and hub.

Designing SoCs for USB Type-C Products

http://webinar.techonline.com/19414?keycode=CAA1CC&cmp=WEBR-dwip100407-HPW

Understand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.

Design, Test & Repair Methodology for FinFET-based Memories

http://webinar.techonline.com/19654?keycode=CAA1CC&cmp=WEBR-dwip100408-HPW

Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.

Choosing the Optimal Multiprotocol PHY IP for Your SoC

http://webinar.techonline.com/19668?keycode=CAA1CC&cmp=WEBR-dwip100413-HPW

Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.

Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and ...

http://webinar.techonline.com/19732?keycode=CAA1CC&cmp=WEBR-dwip100412-HPW

Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.

Implementing Next-Generation Vision Capabilities to Enhance Your SoC Designs

http://webinar.techonline.com/19737?keycode=CAA1CC&cmp=WEBR-dwip100442-HPW

Learn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.