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Enabling DNNs at the Extreme Edge: Co-optimize Circuits, Architectures & ...

January 22, 2021 - Learn how to optimize systems for minimum latency and maximum energy efficiency.

Trends for Embedded Vision & AI IP in Edge Applications

January 22, 2021 - The latest trends in ML for the edge including new models and techniques.

SemiEngineering: IP Safe Enough To Use In Cars

December 07, 2020 - In this video Jody Defazio, vice president of IP quality and functional safety at Synopsys and Ed Sperling discuss the different ASIL levels in safety-critical designs.

Designing Your Own Processor - Introduction to Synopsys ASIP Designer

December 02, 2020 - ASIP Designer: The Efficient Way to Design, Implement, Program and Verify Your Custom Processor

AI SoC Chats: Scaling AI Systems with Die-to-Die Interfaces

November 02, 2020 - Understand the trends around scaling AI SoCs and systems while minimizing latency and power by using die-to-die interfaces.

Accelerate Automotive Certification with Synopsys Functional Safety Test ...

November 02, 2020 - With the Synopsys Functional Safety Test Solution architecture, designers of automotive SoCs can integrate an automated, end-to-end BIST solution to accelerate ISO compliance and time-to-market.

AI SoC Chats: Protecting Data with Security IP

November 02, 2020 - Understand the threat profiles and security trends for AI SoC applications, including how laws and regulations are changing to protect the private information and data of users.

Synopsys and Intel Full System PCIe 5.0 Interoperability Success

October 15, 2020 - This video demonstrates industry's first successful system-level PCI Express (PCIe) 5.0 interoperability between the Synopsys DesignWare Controller and PHY IP for PCIe 5.0 and Intel Xeon Scalable ...

112G SerDes Reliability

October 14, 2020 - This video explains what is acceptable channel loss, and how density can affect performance, power and noise.

Demo: Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP

September 24, 2020 - See ARC EM9D Processors run a handwriting character recognition neural network graph to infer the letter that is written.