Sino Wealth selected Synopsys' silicon-proven DesignWare Bluetooth PHY IP because it met their key design requirements and quality standards. The DesignWare Bluetooth PHY IP offered better ...
Using the ARC EM5D processor-based Smart Data Fusion IP Subsystem and MetaWare Development Toolkit, PLSense quickly and easily integrated their design and achieved first-pass silicon success.
After researching the portfolios of multiple vendors, eWBM selected the Synopsys DesignWare tRoot Secure Hardware Root of Trust, TRNG and SPAcc IP.
Mellanox chose DesignWare® Interfaces, Processors, Embedded Memories and Logic Libraries for their new processor architecture with first-pass silicon success.
The DesignWare AEON FTP Trim NVM IP was used for trimming purposes to adjust sensing values, minimize chip-to-chip variations and improve yield.
Inuitive had a small engineering team focused on the areas that differentiated their NU3000 processor, and selected Synopsys DesignWare USB 3.0, DDR, and MIPI IP after evaluating multiple vendors ...
By using Synopsys’ DesignWare UFS, UniPro and M-PHY IP, optimized for power and performance, we were able to integrate the IP in two weeks, speed our design schedule by six months and achieve ...
Fuji Xerox selected Synopsys’ ASIP Designer, the industry’s leading ASIP design tool environment.
MegaChips chose Synopsys’ DesignWare SATA Device Controller and PHY IP, which met all of their requirements.
Marvell chose Synopsys’ STAR Memory System due to its MMB processor and Yield Accelerator.