IP Resources

Sort by

Synopsys Suggests

How IP-Enabled SoC Design Is Driving Growth Across All Aspects of Dynamic and...

The use of silicon-proven IP is a well-established practice in the world of chip design. In fact, this timesaving and quality-enhancing method to develop complex systems-on-chip (SoCs) is being ...

What Is a Multi-Die Design--and What's Driving Its Growing Popularity?

The semiconductor industry’s relentless drive to achieve increasingly aggressive power, performance, and area (PPA) targets is being further pushed by some burgeoning applications. Indeed, ...

What’s Driving the Demand for 200G, 400G, and 800G Ethernet?

It’s all about bandwidth these days – fueling hyperscale data centers that support high-performance and cloud computing applications. It’s what enables you to stream a movie on your smart TV while ...

Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and ...

July 15, 2021 - Learn how to implement a reliable 112G die-to-die interface in multi-die SoCs while maintaining the required low-latency using a single controller and PHY IP solution.

Anatomy of an Integrated Ethernet PHY IP for High Performance Computing SoCs

July 14, 2021 - Learn about the Ethernet PHY used in HPC SoCs and how an integrated MAC+ PHY IP accelerates path to compliance and time-to-design

Complete Die-to-Die IP Solution: Use Cases and Requirements

July 14, 2021 - Learn about the complete Die-to-Die IP solution, uses cases, requirements and how to address the challenges of multi-die SoCs

SemiEngineering: Best 112G SerDes IP Architecture

July 08, 2021 - Getting the right mix of analog and digital blocks for best performance, lowest power, and smallest area.

SemiWiki: Die-to-Die Connections Crucial for SOCs built with Chiplets

June 25, 2021 - If you ascribe to the notion that things move in circles, or concentrically, the move to die-to-die connectivity makes complete sense. Just as multi-chip modules (MCM) were the right technology ...

ChipEstimate: Tightly-Coupled Analog and DSP Architecture for Best 112G ...

June 22, 2021 - Getting the right mix of analog and digital blocks for best performance, lowest power, and smallest area.

How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity

In this blog post, we’ll discuss how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can ...