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65LPe-Common Platform Datasheet

Broad portfolio of HS, HD and LP memory compilers and a full set of logic libraries optimized for CP 65LPe

ARC microDMA Controller for DesignWare ARC EM Processors Datasheet

The μDMA controller is a fast, low energy optimized option for DesignWare® ARC® EM Processors to allow fast DMA transfers with low gate count and low power consumption.

ARC SEM Family of Security Processors Datasheet

The DesignWare® ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, ...

ASIP Designer - Application-Specific Processor Design Made Easy Brochure

Synopsys’ ASIP Designer and MP Designer tools enable SoC designers to build multicore SoCs with application-specific instruction set processors (ASIPs).

ASIP Designer: Design Tool for Application-Specific Instruction-Set ...

ASIP Designer is a tool suite for the design and verification of application-specific instruction-set processors (ASIPs).

ASIP Programmer: Software Development Kit for Proprietary Processors Datasheet

ASIP Programmer enables software developers to easily take advantage of the unique & specialized architectural features available with the proprietary processor architecture

DesignWare 16- 28-nm High-Speed Data Converter IP Datasheet

Complete portfolio for analog interfaces in 16-nm and 28-nm processes includes high-speed ADCs and DACs, PLL, and general-purpose ADCs and DACs

DesignWare AMBA IP with coreAssembler Datasheet

DesignWare Library IP with coreAssembler uses assembly technology targeted at both AMBA 3 AXI™ and AMBA 2 AHB/APB™ subsystems to automate design creation and initial subsystem validation, reducing ...

DesignWare ARC 600 Family Datasheet

The DesignWare® ARC® 600 family of configurable cores is designed for embedded control, computation and DSP tasks in system-on-chips (SoCs) for consumer, networking, automotive and many othermarkets.