Broad portfolio of HS, HD and LP memory compilers and a full set of logic libraries optimized for CP 65LPe
The μDMA controller is a fast, low energy optimized option for DesignWare® ARC® EM Processors to allow fast DMA transfers with low gate count and low power consumption.
The DesignWare® ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, ...
Synopsys’ ASIP Designer and MP Designer tools enable SoC designers to build multicore SoCs with application-specific instruction set processors (ASIPs).
ASIP Designer is a tool suite for the design and verification of application-specific instruction-set processors (ASIPs).
ASIP Programmer enables software developers to easily take advantage of the unique & specialized architectural features available with the proprietary processor architecture
Complete portfolio for analog interfaces in 16-nm and 28-nm processes includes high-speed ADCs and DACs, PLL, and general-purpose ADCs and DACs
DesignWare Library IP with coreAssembler uses assembly technology targeted at both AMBA 3 AXI™ and AMBA 2 AHB/APB™ subsystems to automate design creation and initial subsystem validation, reducing ...
The DesignWare® ARC® 600 family of configurable cores is designed for embedded control, computation and DSP tasks in system-on-chips (SoCs) for consumer, networking, automotive and many othermarkets.