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ARC SEM Family of Security Processors Datasheet

The DesignWare® ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, ...

Architecture and Design Techniques for Embedded Deep Learning

March 25, 2020 - Embedding deep learning at the edge is challenging due to the huge computational and memory requirements and the algorithmic diversity of modern vision and sensing tasks. Tom describes the ...

Artosyn Selects Synopsys DesignWare Security IP for Drone SoC

September 05, 2018 - Comprehensive Security IP Solution with Hardware Root of Trust Delivers High Level of Protection During SoC Power Off, Power Up, and Runtime

Ashling Opella-XD and Ultra-XD for ARC Debug and Trace

January 07, 2020 - Find out how Ashling’s debug tools work with Synopsys’ ARC MetaWare Development Toolkit to provide high-performance real-time trace capabilities for ARC processors

ASIP Designer - Application-Specific Processor Design Made Easy Brochure

Synopsys’ ASIP Designer and MP Designer tools enable SoC designers to build multicore SoCs with application-specific instruction set processors (ASIPs).

ASIP Designer: Design Tool for Application-Specific Instruction-Set ...

ASIP Designer is a tool suite for the design and verification of application-specific instruction-set processors (ASIPs).

ASIP Programmer: Software Development Kit for Proprietary Processors Datasheet

ASIP Programmer enables software developers to easily take advantage of the unique & specialized architectural features available with the proprietary processor architecture

Assessing ESD Sensitivity of Interface IP Using Charged Device Model

This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM ...