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Compute Express Link (CXL) Controller IP Datasheet

September 11, 2019 - The DesignWare® Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device or host, and can be configured for dual mode applications.

7-nm DesignWare 56G Ethernet PHY IP Performance Results

September 04, 2019 - This video shows the performance and capabilities of Synopsys’ DesignWare 56G Ethernet PHY IP in 7-nm FinFET process.

What Designers Need to Know About DDR5 and LPDDR5

October 01, 2019 - If you are designing SoCs that require high-performance, low-power memory technologies to specifically meet the needs of your applications such as mobile, automotive, and AI, then you must attend ...

Best Practices for Traceabilty of Functional Safety Requirements In ...

August 20, 2019 - Automotive functional safety systems continue to incorporate complex features to meet wide range of consumer demands. Developing functional safety systems, including all the components such as the ...

Synopsys Demo of ASIL-D Ready DesignWare ARC EV6x Embedded Vision Processor ...

August 12, 2019 - Designing automotive SoCs? This new video shows the award-winning DesignWare ARC EV6x processor IP for safety-critical applications used for drowsiness detection, object detection, and lane detection.