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Synopsys Accelerates Development of System-On-Chip Designs With Complete IP ...

July 15, 2009 - High-Quality DesignWare IP for PCI Express 3.0 Delivers 8.0 GT/s for High-Performance Enterprise Computing Systems

Synopsys' Next-Generation DesignWare Data Converter IP Delivers 50 Percent ...

March 21, 2011 - High-performance 10/12-bit ADCs and 14-bit DACs Enable Easy Integration into Broadband Wireless and Wireline Communication SoCs

Synopsys Unveils Industry's First Complete Audio IP Subsystem

March 26, 2012 - Integrated, Configurable Hardware and Software Solution Enables "Drop-in" Audio Functionality Supporting Latest Audio Standards

Synopsys DesignWare IP for PCI Express Used as the Gold Standard in Intel Lab...

August 14, 2008 - Proven Interoperability Lowers Risk of Integrating PCI-SIG I/O Virtualization Technology into Enterprise Computing SoCs

Synopsys Enhances DesignWare DDR PHY IP with Service to Verify Signal Integrity

February 25, 2009 - Customized Report to Help Designers Verify DDR3/2 Timing Budgets and Ensure Electrical Signaling Robustness

Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and ...

September 09, 2009 - DesignWare DDR3/2 PHY and Controller IP Address Both Performance and Low Power Enhancements Planned for the DDR3 SDRAM Standard

DesignWare MIPI C-PHY/D-PHY IP Performance at 24 Gbps

August 14, 2020 - This video features the DesignWare MIPI C-PHY/D-PHY IP interoperating with an image sensor in C-PHY mode up to 3.5 Gsps per trio and D-PHY mode up to 4.5 Gbps per lane, available in FinFET ...

Break Free from Wi-Fi: Create Secure, Global, Cellular Devices with iSIM

June 18, 2019 - In this webinar, Truphone & Synopsys describe the crucial concerns around security, simplicity and reliable connectivity to create a truly scalable solution for secure, global mobile IoT deployments.

How to Achieve Faster, More Accurate Data Throughput with Advanced ...

January 16, 2020 - Today’s signal processing applications such as RADAR/LiDAR, sensor fusion, and baseband communications processing require massive parallel processing capabilities that traditional DSPs cannot ...

Ensuring Known Good Dies in SiPs with Die-to-Die PHY IP

January 28, 2021 - Learn how high-performance computing (HPC) SoC designers leverage SerDes-based USR/XSR or parallel-based HBI die-to-die PHY IP solutions to identifying known good dies.