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DesignWare 11-bit, 20 MSPS, 2.5V DAC with Voltage Mode Output Datasheet

11-bit 20 MHz current steering DAC IP coupled to a current to voltage converter, instantiated in a 65-nm 1P6M CMOS technology supplied at 1.2/2.5 V.

DesignWare 12-bit, 20 MSPS, 1.8V DAC with Voltage Buffer Datasheet

High-performance, ultra-low power and compact 12-bit 20 MHz current steering DAC IP coupled to a current to voltage converter, instantiated in a 28-nm CMOS technology supplied at 1.8 V/0.9 V.

DesignWare 12-bit, 160 MSPS, 2.5V Dual Current Steering DAC Datasheet

High performance, compact 12-bit 160 MHz current steering IQ-DAC IP instantiated in a 65-nm CMOS technology supplied at 1.2 / 2.5 V.

DesignWare 12-bit, 160 MSPS, 2.5V Dual Current Steering DAC Datasheet

High performance, compact 12-bit 160 MHz current steering IQ-DAC IP instantiated in a 65-nm CMOS technology supplied at 1.2 / 2.5 V.

DesignWare DDR2/3-Lite PHY Datasheet

The DesignWare DDR2/3-Lite/mDDR PHY is a complete, silicon-proven, physical (PHY) layer IP interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in-Package applications requiring ...

DesignWare DDR3/2 PHY Datasheet

The DesignWare DDR3/2 PHY is a complete, silicon-proven, physical (PHY) layer IP interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in- Package applications requiring ...

DesignWare DDR4/3 PHY IP Datasheet

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance ...

DesignWare DDR4 multiPHY Datasheet

The Synopsys DesignWare DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on-chip (SoC), and system-in-package applications ...

DesignWare DDR Complete Solution Datasheet

DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, ...

DesignWare Gen 2 DDR multiPHY Datasheet

The Synopsys DesignWare Gen 2 DDR multiPHY is a complete physical interface solution for interfacing to many different kinds of JEDEC standard mobile SDRAMs and PC/consumer SDRAMs.