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Optimizing Analog Sensor Interfaces with Integrated Data Converter IP

February 28, 2018 - Learn how to simplify your sensor system design with an integrated data converter IP solution that enables low-power & compact IoT SoCs for general purpose MCUs and other edge devices

Mellanox and Synopsys Demonstrate Industry’s First PCIe 4.0 Interoperability

March 02, 2015 - Mutual Technology Leadership Lowers Risk for Designers Implementing16GT/s PCI Express Protocol

Optimizing SMIC 40LL & 40ULP Designs for Speed & Energy Efficiency - Taiwan

March 13, 2018 - Learn how to optimize power and performance in IoT SoCs using DesignWare Embedded Memories & Logic Libraries in SMIC processes

Synopsys Embedded Vision Processor IP Quadruples Neural Network Performance ...

June 26, 2017 - Enhanced DesignWare EV6x Family Delivers Up to 4.5 TeraMACs/sec for Real-Time Vision Processing

Synopsys’ New DesignWare ARC HS Processors for Next-Generation Embedded Systems

November 05, 2013 - New Performance-Efficient Design Optimized for Maximum DMIPS/mm2 and DMIPS/milliwatt

DesignWare DDR2/3-Lite PHY Datasheet

The DesignWare DDR2/3-Lite/mDDR PHY is a complete, silicon-proven, physical (PHY) layer IP interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in-Package applications requiring ...

DesignWare DDR3/2 PHY Datasheet

The DesignWare DDR3/2 PHY is a complete, silicon-proven, physical (PHY) layer IP interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in- Package applications requiring ...

DesignWare DDR4/3 PHY IP Datasheet

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance ...

DesignWare DDR4 multiPHY Datasheet

The Synopsys DesignWare DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on-chip (SoC), and system-in-package applications ...