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Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer

This white paper will explain the concept of the read reorder buffer and explain how a read reorder buffer can improve memory bandwidth.

Achieve USB 3.1 Interoperability with DesignWare® USB 3.1 IP

December 05, 2017 - Join Eric Huang as he demonstrates how Synopsys ensures USB 3.1 Host PHY and Controller compatibility with the USB-IF standard, and goes beyond the standard to help make your end products as ...

Achronix Selects Synopsys’ Leading DesignWare IP Solutions to Accelerate ...

March 26, 2020 - Silicon-Proven DesignWare IP for PCI Express 5.0 and DDR4 Delivers Low Latency and High Bandwidth for Data-Intensive Workloads

Addressing Automotive Safety Requirements with ASIL D Ready Vision Processor IP

May 17, 2018 - Learn about the new ASIL D Ready DesignWare EV6x Embedded Vision Processor IP with Safety Enhancement Package (SEP) for AI-enabled automotive SoCs. The EV6x with SEP helps designers accelerate ISO ...

Addressing Flash Storage Design Challenges with DesignWare® ARC® ...

August 01, 2017 - Learn about challenges engineers face when designing flash storage controllers and find out the unique features Synopsys' DesignWare® ARC® processors offer that enable designers to get the best ...

Addressing IoT Connectivity Challenges with Low-power NB-IoT Modem ...

April 16, 2020 - Low power IoT connectivity requires modem chipsets and integrated wireless options to enable cost-effective deployment. Narrow-band IoT (NB-IoT) is a key 3GPP cellular communication standard that ...

Addressing IP Integration & Software Development Challenges to Accelerate SoC...

This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality ...

Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP

This paper describes the main power versus resolution trade-offs existing in the design of pipeline ADCs.

Addressing the Rapid Growth of the Storage Market with ARC® Processors

June 22, 2017 - Learn about trends in the storage market and find out how Synopsys' performance-efficient DesignWare® ARC® EM and HS processors enable engineers to create adaptable and scalable SSD designs that ...

Addressing Three Critical Challenges of USB Type-C Implementation

This white paper describes these key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.