October 03, 2019
September 30, 2019 - The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.
September 30, 2019 - The multi-channel DesignWare® PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth.
September 30, 2019 - This video shows the transmitter and receiver testing of Synopsys’ DesignWare 112G Ethernet PHY IP in TSMC’s N7 process.
September 26, 2019 - Interface and Foundation IP Enables Next Wave of Low-Power Mobile and High-Performance Cloud Computing SoCs on TSMC's N5P Process
September 25, 2019
September 24, 2019 - Gary Ruggles, senior staff product marketing manager at Synopsys, talks with Semiconductor Engineering about the Compute Express Link standard, why it’s important for high bandwidth in AI/ML ...
September 24, 2019 - DesignWare 112G Ethernet PHY on TSMC’s N7 Process Enables True Long Reach Channels for 800G Networking Applications