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DesignWare Multi-Protocol 32G PHY IP Datasheet

September 30, 2019 - The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.

DesignWare PHY IP for PCI Express 5.0 and CXL Datasheet

September 30, 2019 - The multi-channel DesignWare® PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth.

DesignWare 112G Ethernet PHY IP in TSMC N7 Process

September 30, 2019 - This video shows the transmitter and receiver testing of Synopsys’ DesignWare 112G Ethernet PHY IP in TSMC’s N7 process.

Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC ...

September 26, 2019 - Interface and Foundation IP Enables Next Wave of Low-Power Mobile and High-Performance Cloud Computing SoCs on TSMC's N5P Process

The New CXL Standard

September 24, 2019 - Gary Ruggles, senior staff product marketing manager at Synopsys, talks with Semiconductor Engineering about the Compute Express Link standard, why it’s important for high bandwidth in AI/ML ...

Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for ...

September 24, 2019 - DesignWare 112G Ethernet PHY on TSMC’s N7 Process Enables True Long Reach Channels for 800G Networking Applications