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DesignWare Ethernet Quality-of-Service Datasheet

The silicon-proven Ethernet QoS IP implements the link layer of an OSI Ethernet system, with support for advanced IEEE standards such as the Audio Video Bridging, Data Center Bridging and TCP/IP ...

DesignWare IP for PCI Express Complete Solution Datasheet

The complete silicon-proven DesignWare IP solution, consisting of configurable digital controllers, PHYs and verification IP, is compliant with the PCI Express (PCIe) 4.0, 3.1, 2.1, and 1.1 ...

Synopsys' New Enhanced Security Package for ARC HS Processors Protects ...

February 27, 2019 - Enables Development of Isolated, Secure Environments for High-Performance Applications

Enhanced Security Package for ARC HS Processor Family Datasheet

February 27, 2019 - The Enhanced Security Package option available for DesignWare® ARC® HS family processors enables designers to create a secure environment that protects their systems and software from evolving ...

Synopsys and Palma Ceia SemiDesign Collaborate to Develop a Complete ...

February 25, 2019 - Combination of Synopsys' ARC EM Processor with Palma Ceia's Silicon-Proven RF Transceiver Facilitates LTE Cat NB2 SoC Implementations

Which DDR SDRAM Memory to Use and When

Memory performance is a critical component for achieving the desired system performance in a wide range of applications from cloud computing and artificial intelligence (AI) to automotive and mobile.