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Enabling USB 2.0 in Advanced Process Nodes Using DesignWare eUSB2 IP

June 26, 2019 - Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.

Qualified MIPI IP for Automotive ADAS SoCs

June 25, 2019 - See how MIPI CSI-2, DSI, and I3C interfaces offer efficient and high-performance solutions for automotive ADAS and infotainment applications by allowing fast image processing between the sensor and...

New Challenges For Data Centers

June 21, 2019 - Semiconductor Engineering Video: New Challenges for Data Centers and the Need to Transition to 400G Ethernet Links

DesignWare PHY IP Meeting the PCIe 5.0 Rev. 1.0 Specification

June 21, 2019 - This video features Synopsys’ DesignWare PHY IP for PCI Express 5.0 meeting the Rev. 1.0 specification’s channel performance and jitter tolerance.

Holes In AI Security

June 14, 2019 - Learn about why security is lacking in AI, why AI is especially susceptible to Trojans, and why small changes in training data can have big impacts on many devices.

DAC 2019 Video: Importance of Selecting the Right Memory Interface IP

June 12, 2019 - Synopsys at DAC 2019 by Graham Allan, Sr. Manager, Product Marketing at Synopsys

DAC 2019 Interview: Automotive and Influence of AI

June 12, 2019 - Synopsys at DAC 2019 : Automotive and Artificial Intelligence By Ron DiGiuseppe, Automotive IP Segment Manager at Synopsys

AC 2019 Interview: Functional Safety Requirement

June 12, 2019 - Interview with Yervant Zorian from Synopsys at DAC 2019. Yervant discusses functional safety with ChipTV's Sean O'Kane at DAC in Las Vegas.

Selecting the right DDR Memory IP for Greatest Impact

May 01, 2019 - SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications

Developing RADAR for ADAS Applications using DesignWare® ARC® Processors

April 26, 2019 - Learn about Synopsys’ Processor Solutions that meet high-computation and specialized processing requirements, enabling design teams to create highly-efficient and differentiated SoCs for RADAR ...