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AI SoC Chats: Host Processor Interconnect IP for AI Accelerators

July 31, 2020 - To support host-to-AI accelerator connectivity, AI chipsets can use PCI Express, CCIX, and/or CXL, and each have their benefits. Learn how to find the right interconnect for your AI SoC design.

AI SoC Chats: Primitive Math IP for AI

July 31, 2020 - Learn about the market trends and challenges around primitive math functions (floating point and integer math) in AI chipset development, and how DesignWare IP can help.

AI SoC Trends: IP for In-Memory / Near-Memory Compute

July 27, 2020 - AI chipsets are data hungry and have high compute intensity, leading to potential power consumption issues. Join Synopsys Fellow Jamil Kawa to learn how in-memory or near-memory compute, 3D ...

Product Update: New USB4 IP Solution

July 20, 2020 - Are you ready for USB4? Join Gervais Fong and Eric Huang to learn more about this new 40Gbps standard and Synopsys DesignWare IP that helps bring your USB4-enabled design to market faster.

Available DesignWare MIPI D-PHY IP for 22-nm Process

July 10, 2020 - This video describes the advantages of Synopsys' MIPI D-PHY IP for 22-nm process, available in RX, TX, bidirectional mode, 2 and 4 lanes, operating at 10 Gbps. The IP is ideal for IoT, automotive, ...

Product Update: High-Performance DesignWare Memory Interface IP

June 25, 2020 - Get the latest update on Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E and how you can enable your DRAMs with the highest-performance, lowest-power, and lowest-area IP ...

Product Update: Protect IoT SoCs with DesignWare OTP NVM IP

June 25, 2020 - Join Krishna Balachandran in this discussion on securing SoC data and IoT connections using Synopsys DesignWare OTP NVM IP. With more than 12 years of development and deployment by 500+ customers, ...

Product Update: Highly Optimized DesignWare 112G/56G Ethernet PHY IP

June 19, 2020 - Get the latest update on Synopsys’ PAM-4 DesignWare 112G/56G Ethernet PHY IP with optimized power, performance, and area, enabling true long reach connectivity in 400G/800G high-performance ...

Product Update: Advances in DesignWare Die-to-Die PHY IP

June 08, 2020 - Hear the latest about Synopsys' DesignWare MIPI Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP, available in advanced FinFET processes, addresses the ...

Product Update: DesignWare IP for PCIe 5.0

June 08, 2020 - Get the latest update on Synopsys' DesignWare Controller and PHY IP for PCIe 5.0 and how the low-latency, compact, power-efficient, and silicon-proven solution can enable your SoCs while reducing ...