November 24, 2016
July 15, 2020 - High-Quality DesignWare Interface and Processor IP for Efficient Real-Time Connectivity and Machine Learning Processing Accelerate Design Schedule and Lower Risk
January 30, 2019 - Solutions Supporting PCI Express 3.0/4.0/5.0 and Ethernet PAM4 Among Demonstrations to be Given by Global Test Leader at Premier Engineering Show
November 07, 2016
The challenges of embedded memory test and repair are well known, including maximizing fault coverage to prevent test escapes and using spare elements to maximize manufacturing yield. With the ...
This white paper explains how to characterize PCIe 5.0 PHY designs to avoid issues such as signal integrity and reliability prior to manufacturing.
This white paper describes a methodology for jitter tolerance testing without using the controller to negotiate a link. In addition, the paper outlines a procedure for calibrating the stressed eye ...
Understand the functional safety, reliability and quality standards for automotive ICs, and how embedded memories and logic libraries can influence your product’s success.
Mixed-signal PHY IP, including trends and design challenges.Navraj Nandra