System architects must make good system-level choices to get the best results from the analog signal-conversion IP — a crucial factor in gaining a competitive edge in any market.
In this paper we will explore three important determinants of IP quality.
This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain.
The latest HDMI 1.4 specification makes new provisions to penetrate into the mobile consumer electronics market and incorporates an Ethernet Channel into the HDMI cable, avoiding the need for a ...
This document summarizes coding guidelines addressing the synthesis of datapaths.
This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains.
This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another.
This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys’ complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target ...
This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital intellectual property (IP) core into a Gigabit Ethernet design.
This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.