IP Resources

Sort by

Synopsys Suggests

Agere/Synopsys: Integrating a PCI Express Digital IP Core into a Gigabit ...

This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital intellectual property (IP) core into a Gigabit Ethernet design.

The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator

This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.

Solving the Integration Challenges for USB-Enabled Designs

SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB ...

Understanding the Fundamentals of PCI Express

The objective of this whitepaper is to equip the reader with a broad understanding of PCI Express and the design challenges essential to successful PCIe implementation.

Life Begins at 65, Unless You Are Mixed-Signal?

The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm ...

Implementing Floating-Point IP for the Right Accuracy and Quality of Results ...

This whitepaper describes several types of flexible tradeoffs available to designers, including the benefits of specifying complex floating-point operations rather than multiple separate operations.

DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for ...

This whitepaper provides a brief history of the SDRAM, discusses the design considerations for implementing a DDRn controller and PHY, and describes how a complete IP solution can help speed time ...

Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies

After an introduction to circuit and process trends in deep sub-micron technologies, this article will present a complete protocol solution using the high speed memory DDR2 interface as an example.

High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor

In this paper, we will discuss how to select a third party IP vendor, how to verify third party IP, and some of the gotcha’s when integrating third party IP, with a special focus on the ...

Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler

This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable ...