This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable ...
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability ...
Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at ...
September 26, 2005 - Testing Conducted With Synopsys' Wireless USB Device Controller IP and Alereon's WiMedia Ultra-Wideband PHY
September 26, 2005 - Early IP Availability From Synopsys Drives Wireless USB Integration Into Next Generation SoCs
September 21, 2005 - Addition Enables Easy Adoption of AMBA 3 AXI Protocol with Automated Subsystem Assembly and Comprehensive Set of Synthesizable and Verification IP
August 23, 2005 - Demo at Intel Developer Forum Shows Two-Way Transfer of Large Multimedia Files using the USB-IF's Wireless USB and WiMedia UWB Platform
June 08, 2005 - Synopsys to Deliver Complete System to Implementation Solution for Power Architecture Designs
June 06, 2005 - DesignWare Digital Controller Cores and PHY IP Available Today for the PCI Express 1.1 Standard
June 06, 2005 - Proven SATA Verification IP Lowers Risk and Speeds Verification for SoC Designers