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DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for ...

This whitepaper provides a brief history of the SDRAM, discusses the design considerations for implementing a DDRn controller and PHY, and describes how a complete IP solution can help speed time ...

Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies

After an introduction to circuit and process trends in deep sub-micron technologies, this article will present a complete protocol solution using the high speed memory DDR2 interface as an example.

High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor

In this paper, we will discuss how to select a third party IP vendor, how to verify third party IP, and some of the gotcha’s when integrating third party IP, with a special focus on the ...

Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssemblerΓäó

This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable ...

Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design

Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability ...

Synopsys and Alereon Demonstrate Interoperability for Certified Wireless USB ...

Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at ...

Building a USB 2.0 Device AMBA Subsystem with DesignWare IP

By using standard on-chip interfaces like the AMBA 2.0 specification, you can greatly reduce the amount of time it takes to get an entire subsystem configured to handle the new speed and data ...