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Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssemblerΓäó

This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable ...

Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design

Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability ...

Synopsys and Alereon Demonstrate Interoperability for Certified Wireless USB ...

Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at ...

Building a USB 2.0 Device AMBA Subsystem with DesignWare IP

By using standard on-chip interfaces like the AMBA 2.0 specification, you can greatly reduce the amount of time it takes to get an entire subsystem configured to handle the new speed and data ...